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QL5030 QuickPCI Data Sheet
* * * * * * 33 MHz/32-bit PCI Target with Embedded Programmable Logic
and Dual Port SRAM
1.0 Device Highlights
High Performance PCI Controller
* 32-bit / 33 MHz PCI Target * Zero-wait state PCI Target Provides 132 * * * * * * * * * * * * * Programmable Interrupt Generator * I2O Support with Local Processor * Mailbox Register Support
MB/s Transfer Rates Programmable Back-end Interface to Optional Local Processor Independent PCI bus (33 MHz) and Local Bus (up to 160 MHz) Clocks Fully Customizable PCI Configuration Space Configurable FIFOs with Depths up to 128 Reference Design with Driver Code (Win 95/98/Win 2000/NT4.0) Available PCI v2.2 Compliant Supports Type 0 Configuration Cycles 3.3V, 5V Tolerant PCI Signaling Supports Universal PCI Adapter Designs 3.3V CMOS in 144-pin TQFP Supports Endian Conversions Unlimited/Continuous Burst Transfers Supported
Programmable Logic
* 24K System gates / 266 Logic Cells * 9,216 RAM bits, 71 I/O pins * 250 MHz 16-bit counters, 275 MHz
Datapaths, 160 MHz FIFOs * All Back-end Interface and Glue-logic can be Implemented on Chip * 4 64-deep FIFOs (2 RAMs each) or 2 128deep FIFOs (4 RAMs each) or a Combination that Requires 8 or less QuickLogic RAM Modules * (2) 32-bit Busses Interface between the PCI Controller and the Programmable Logic
PCI Bus - 33 MHz 32 Bits (Data and Address)
PCI CONTROLLER Target Controller High Speed Data Path
Extendable PCI Functionality
* Support for Configuration Space from 0x40 * * * *
to 0x3FF Multi-Function, Expanded Capabilities, & Expansion ROM Capable Power Management, Compact PCI, Hot-swap/Hot-plug Compatible PCI v2.2 Power Management Spec Compatible PCI v2.2 Vital Product Data (VPD) Configuration Support
32
32
INTERFACE
Config Space
High Speed Logic Cells 24K Gates
160 MHz FIOFs
71 User I/O
PROGRAMMABLE LOGIC
Figure 1: QL5030 Block Diagram
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QL5030 QuickPCI Data Sheet
2.0 Architecture Overview
The QL5030 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with 24,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MB/s). The programmable logic portion of the device contains 266 QuickLogic Logic Cells, and 8 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs. See the RAM section of this data sheet for more information. The QL5030 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. This device also supports the Win'98 and PC'98 standards. The QL5030 device features 3.3-volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3.3-volt systems and is fully compatible with 3.3V, 5V or Universal PCI card development.
2.1 PCI Interface
The PCI target is PCI 2.2 compliant and supports 32-bit/33 MHz operation. It is capable of zero waitstate infinite-length read and write transactions (132 MBytes/second). Transaction control is available via the user interface as retries, wait-states, or premature transaction termination may be induced if necessary. The PCI configuration registers are implemented in the programmable region of the device, leaving the designer with ample flexibility to support optional features. The QL5030 device supports maximum 32-bit PCI transfer rates, so many applications exist which are ideally suited to the device's high performance. High-speed data communications, telecommunications, and computing systems are just a few of the broad range of applications areas that can benefit from the high speed PCI interface and programmable logic.
2.2 PCI Configuration Space
The QL5030 supports customization of required Configuration Registers such as Vendor ID, Device ID, Subsystem Vendor ID, etc.. QuickLogic provides a reference Configuration Space design block. Since the PCI Configuration Registers are implemented in the programmable region of the QL5030, the designer can implement optional features such as multiple 32-bit Base Address Registers (BARs) and multiple functions, as well as support the following PCI commands: I/O Read, I/O Write, Memory Read, Memory Write, Config Read (required), Configuration Write (required), Memory Read Multiple, Memory Read Line, and Memory Write and Invalidate. Additionally, the device supports Extended Capabilities Registers, Expansion ROMs, power management, CompactPCI hot-plug/hot-swap, Vital Product Data, I20, and mailbox registers.
2.3 Address and Command Decode
PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5030. QuickLogic provides a reference Address Register/Counter and Command Decode block.
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QL5030 QuickPCI Data Sheet
3.0 RAM Architecture Overview
The RAM modules in the programmable region can be used to create configurable 32-bit FIFOs. Each 32-bit FIFO can be independently assigned to Target address space for read pre-fetch or write posting. Using the 8 QuickLogic RAM modules, the combinations include:
* 4 independent 64-deep FIFO (2 RAMs each),
or * 2 independent 128-deep FIFOs (4 RAMs each), or * a combination of the above that requires 8 or less QuickLogic RAM Modules Asynchronous FIFOs (with independent read and write clocks) are also supported.
Figure 2: Graphical Interface to create FIFO
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QL5030 QuickPCI Data Sheet
4.0 Internal PCI Interface
The symbol used to connect to the PCI interface of the QL5030 is shown below. This symbol is used in schematic or mixed schematic/HDL design flows in the QuickWorks software.
PCIT32 PCI Pads CLK RSTN IDSEL CBEN[3:0] FRAMEN IRDYN PCI Signals AD[31:0] TRDYN DEVSELN STOPN PAR PERN SERRN
PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCIDEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 Usr_Write Cfg_Write Usr_Addr_WrData[31:0] Usr_CBE[3:0] Usr_Adr_Valid Usr_Adr_Inc Usr_Last_Cycle_D1 Usr_TRDYN Usr_STOPN Usr_Devsel Cfg_PERR_Det Cfg_SERR_Sig Usr_RdPipe_Stat[1:0]
Usr_RdData[31:0] Usr_Select Usr_Stop Usr_Rdy
Target
Usr_RdDecode Usr_WrDecode Cfg_RdData[31:0] Cfg_CmdReg6 Cfg_CmdReg8
Figure 3: PCI Interface Symbol
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QL5030 QuickPCI Data Sheet
5.0 Internal Interface Signal Descriptions
Signals used to connect to the PCI interface in the QL5030 are described below. The direction of the signal indicates if it is an input provided by the local interface (I) or an output provided by the PCI interface (O).
Table 1: Internal Interface Signal Descriptions Signal
Usr_Addr_WrData[31:0]
I/O
O
Description
Target address, and data from target writes. During all target accesses, the address will be presented on Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will be active. During target write transactions, this port will also present write data to the PCI configuration space or user logic. PCI command and byte enables. During target accesses, the PCI command will be presented on Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During target read or write transactions, this port will present active-low byte-enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal will be low, indicating that an address is NOT present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer has completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented (by 4) for subsequent data transfers. Note that during write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the back-end logic (regardless of the state of Usr_Rdy). During read transactions, Usr_Adr_Inc will signal to the back-end that the PCI core is ready to accept data. Usr_Adr_Inc and Usr_Rdy both active during a read transaction signals a data transfer between the FPGA and the PCI core (and that the address counter must be incremented). This signal should be driven active when a "user read" command has been decoded from the Usr_CBE[3:0] bus (while Usr_Adr_Valid is active). This command may be mapped from any of the PCI "read" commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. This signal should be driven active when a "user write" command has been decoded from the Usr_CBE[3:0] bus (while Usr_Adr_Valid is active). This command may be mapped from any of the PCI "write" commands, such as Memory Write or I/O Write. This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). This signal will be active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at the beginning of the transaction. The write-enable for individual double-words of data (on Usr_Addr_WrData[31:0]) during a user write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. This signal will be active throughout a configuration write transaction. The write-enable for individual double-words of data (on Usr_Addr_WrData[31:0]) during a configuration write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. Data from the PCI configuration registers, required to be presented to the PCI core during PCI configuration reads. Data from the back-end user logic, required to be presented during PCI reads. Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h).
Usr_CBE[3:0]
O
Usr_Adr_Valid
O
Usr_Adr_Inc
O
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write
O
Cfg_Write
O
Cfg_RdData[31:0] Usr_RdData[31:0]
I I
Cfg_CmdReg8Cfg_CmdReg6 I
(Sheet 1 of 2)
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QL5030 QuickPCI Data Sheet
Table 1: Internal Interface Signal Descriptions (Continued) Signal
Cfg_PERR_Det Cfg_SERR_Sig Usr_TRDYN Usr_STOPN Usr_Devsel Usr_Last_Cycle_D1
I/O
O O O O O O
Description
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). System error asserted on the PCI bus. When this signal is active, the Signaled System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Copy of the TRDYN signal as driven by the PCI target interface. Copy of the STOPN signal as driven by the PCI target interface. Inverted copy of the DEVSELN signal as driven by the PCI target interface. Indicates that the last transfer in a PCI transaction is occurring. Indicates the number of dwords currently in the read pipeline ("00" = 0 elements, "01" = 1 element, "11" = 2 elements). This value is important at the end of a transaction (i.e. when Usr_Last_Cycle_D1 is active) if non-prefetchable memory is being read. Non-prefetchable memory is defined as registers or memory elements whose value changes when they are read. Examples are status registers which are cleared when they are read, or FIFO memories, since consecutive reads from the same address in these elements may not produce the same data values. Used to delay (add wait states to) a PCI transaction when the back end needs additional time. Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock.
RdPipe_Stat[1:0]
O
Usr_Rdy Usr_Stop
I I
(Sheet 2 of 2)
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QL5030 QuickPCI Data Sheet
6.0 Array of Logic Cells
A wide range of additional features complements the QL5030 device. The FPGA portion of the device is 5-volt and 3.3-volt PCI-compliant and can perform high-speed logic functions such as 160 MHz FIFOs. I/O pins provide individually controlled output enables, dedicated input/feedback registers, and full JTAG capability for boundary scan and test. In addition, the QL5030 device provides the benefits of non-volatility, high design security, immediate functionality on power-up, and a single chip solution. The QL5030 programmable logic architecture consists of an array of user-configurable logic building blocks, called logic cells, set beneath a grid of metal wiring channels similar to those of a gate array. Through ViaLink(R) elements located at the wire intersections, the output(s) of any cell may be programmed to connect to the input(s) of any other cell. Using the programmable logic in the QL5030, designers can quickly and easily customize their "back-end" design for any number of applications.
QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 QC QR
AZ
OZ
QZ
NZ
FZ
Figure 4: Logic Cell
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QL5030 QuickPCI Data Sheet
7.0 RAM Module Features
The QL5030 device has eight 1,152-bit RAM modules, for a total of 9,216 RAM bits. Using two "mode" pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks. See Figure 5. The blocks are also easily cascadable to increase their effective width or depth.
RAM Module
MODE[1:0] WA[a:0] WD[w:0] ASYNCRD RA[a:0] RD[w:0]
WE WCLK
RE RCLK
Figure 5: RAM Module
Table 2: RAM Mode Mode:
64x18 128x9 256x4 512x2
Address Buses [a:0]
[5:0] [6:0] [7:0] [8:0]
Data Buses [w:0]
[17:0] [8:0] [3:0] [1:0]
The RAM modules are "dual-ported", with completely independent READ and WRITE ports and separate READ and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE ports support synchronous operation. Each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for asynchronous READ operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 512-deep configurations as large as 16 bits wide in the QL5030 device. A similar technique can be used to create depths greater than 512 words. In this case, address signals higher than the eighth bit are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
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QL5030 QuickPCI Data Sheet
8.0 JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5030 device. Six pins are dedicated to JTAG and programming functions on each QL5030 device, and are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM, is used only for programming.
9.0 Development Tools
Software support for the QL5030 device is available through the QuickWorksT M development package. This turnkey PC-based QuickWorks package, shown in Figure 6, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify LiteT M tool, specially tuned to take advantage of the QL5030 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickToolsT M and PC-based QuickWorks-LiteT M packages are a subset of QuickWorks and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools and QuickWorks-Lite read EDIF netlists and provide support for all QuickLogic devices. QuickTools and QuickWorks-Lite also support a wide range of third-party modeling and simulation tools. In addition, the PC-based package combines all the features of QuickWorks-Lite with the SCS schematic capture environment, providing a low-cost design entry and compilation solution.
QuickWorks Design Software
Third Party Design Entry & Synthesis
Schematic
SCS Schematic Tools
VHDL/ Verilog
Turbo Writer HDL Editor
Mixed-Mode Design
Synplify-Lite HDL Synthesis
Third Party Simulation
QuickTools/QuickChip: Optimize, Place, & Route
Silos & Simulators
Figure 6: QuickWorks Tool Suite
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QL5030 QuickPCI Data Sheet
10.0 DC Characteristics
The DC Specifications are provided in the tables below.
Table 3: Absolute Maximum Ratings VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity
-0.5 to 4.6V -0.5 to 7.0V -0.5V to VCCIO +0.5V 200 mA
DC Input Current ESD Pad Protection Storage Temperature Lead Temperature
20 mA 2000V -65C to +150C 300C
Table 4: Operating Range Symbol Parameter Industrial Min
VCC VCCIO TA K Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Delay Factor -A Speed Grade 3.0 3.0 -40 0.43
Commercial Min
3.0 3.0 0 0.46
Unit
Max
3.6 5.5 85 0.90
Max
3.6 5.25 70 0.88 V V C
Table 5: DC Characteristics Symbol
VIH VIL VOH
Parameter
Input HIGH Voltage Input LOW Voltage
Conditions
Min
0.5VCC -0.5
Max
VCCIO+0.5 0.3VCC
Unit
V V V V
IOH = -12 mA Output HIGH Voltage IOH = -500 mA IOL = 16 mA VOL II IOZ CI IOS ICC ICCIO Output LOW Voltage IOL = 1.5 mA I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [a] VO = GND Output Short Circuit Current [b] VO = VCC D.C. Supply Current [c] D.C. Supply Current on VCCIO VI, VIO = VCCIO or GND VI = VCCIO or GND VI = VCCIO or GND
2.4 0.9VCC 0.45 0.1VCC -10 -10 10 10 10 -15 40 0.50 (typ) 0 -180 210 2 100
V V mA mA pF mA mA mA mA
a. Capacitance is sample tested only. b. Only one output at a time. Duration should not exceed 30 seconds. c. See Application Note 32: Power calculations for QuickLogic devices.
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QL5030 QuickPCI Data Sheet
11.0 AC CHARACTERISTICS at VCC = 3.3V, TA = 25xC (K = 1.00)
To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.
Table 6: Logic Cells Symbol Parameter 1
tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
Propagation Delays (ns) Fanout [a] 2
1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8
3
1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8
4
2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8
8
3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
Table 7: RAM Cell Synchronous Write Timing Symbol Parameter 1
tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [4] 1.0 0.0 1.0 0.0 1.0 0.0 5.0
Propagation Delays (ns) Fanout [a] 2
1.0 0.0 1.0 0.0 1.0 0.0 5.3
3
1.0 0.0 1.0 0.0 1.0 0.0 5.6
4
1.0 0.0 1.0 0.0 1.0 0.0 5.9
8
1.0 0.0 1.0 0.0 1.0 0.0 7.1
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25xC. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
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QL5030 QuickPCI Data Sheet
Table 8: RAM Cell Synchronous Read Timing Symbol Parameter 1
tSRA tHRA tSRE tHRE tRCRD RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 1.0 0.0 1.0 0.0 4.0
Propagation Delays (ns) Fanout 2
1.0 0.0 1.0 0.0 4.3
3
1.0 0.0 1.0 0.0 4.6
4
1.0 0.0 1.0 0.0 4.9
8
1.0 0.0 1.0 0.0 6.1
Table 9: RAM Cell Asynchronous Read Timing Symbol Parameter 1
rPDRD RA to RD [5] 3.0
Propagation Delays (ns) Fanout 2
3.3
3
3.6
4
3.9
8
5.1
Table 10: Input-Only Cells Symbol Parameter 1
tIN tINI tISU tIH tlCLK tlRST tlESU tlEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0
Propagation Delays (ns) Fanout [a] 2
1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0
3
1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0
4
1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0
8
2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0
12
2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0
24
4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5030 QuickPCI Data Sheet
Table 11: Clock Cells Symbols Parameter 1
tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8
Propagation Delays (ns) Loads per Half Column [a] 2
1.2 0.7 0.8
3
1.3 0.7 0.9
4
1.3 0.7 0.9
8
1.5 0.7 1.1
10
1.6 0.7 1.2
12
1.7 0.7 1.3
15
1.8 0.7 1.4
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
Table 12: I/O Cell Input Delays Symbol Parameter 1
tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0
Propagation Delays (ns) Fanout [5] 2
1.6 3.1 0.0 1.0 0.9 2.3 0.0
3
1.8 3.1 0.0 1.2 1.1 2.3 0.0
4
2.1 3.1 0.0 1.5 1.4 2.3 0.0
8
3.1 3.1 0.0 2.5 2.4 2.3 0.0
10
3.6 3.1 0.0 3.0 2.9 2.3 0.0
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QL5030 QuickPCI Data Sheet
Table 13: I/O Cell Output Delays Symbol Parameter 30
tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State 2.1 2.2 1.2 1.6 2.0 1.2
Propagation Delays (ns) Output Load Capacitance (pF) 50
2.5 2.6 1.7 2.0
75
3.1 3.2 2.2 2.6
100
3.6 3.7 2.8 3.1
150
4.7 4.8 3.9 4.2
NOTE: The following loads are used for tPXZ:
tPHZ 1K 5 pF
1K tPLZ 5 pF
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QL5030 QuickPCI Data Sheet
12.0 QL5030 External Device Pins
The QL5030 Device Pins are indicated in Table 14 and Table 15 below. These are pins on the device, some of which connect to the PCI bus, and others that are programmable as user I/O.
Table 14: Pin Type Descriptions Type
IN OUT T/S Input. A standard input-only signal Totem pole output. A standard active output driver Tri-state. A bi-directional, tri-state input/output pin
Description
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the S/T/S PCI system central resource to sustain the inactive state once the active driver has released the signal. O/D Open Drain. Allows multiple devices to share this pin as a wired-or.
Table 15: Device Pins Pin/Bus Name Type
VCC VCCIO GND I/O GLCK/I ACLK/I TDI/RSI* TDO/RCO* TCK TMS TRSTB/RRO* STM IN IN IN T/S IN IN IN OUT IN IN IN IN Supply pin. Tie to 3.3V supply. Supply pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O Ground pin. Tie to GND on the PCB. Programmable Input/Output/Tri-State/Bi-directional Pin. Programmable Global Network or Input-only pin. Tie to VCC or GND if unused. Programmable Array Network or Input-only pin. Tie to VCC or GND if unused. JTAG Data In/Ram Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data for RAM init. JTAG Data Out/Ram Init Clock. Leave unconnected if unused. Connect to Serial EPROM clock for RAM init. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for RAM init. QuickLogic Reserved pin. Tie to GND on the PCB.
Function
NOTE: *See QuickNote 65 on the QuickLogic website for information on RAM initialization.
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QL5030 QuickPCI Data Sheet
13.0 External Device Pins
Table 16: External Device Pins Pin/Bus Name Type
AD[31:0] CBEN[3:0] T/S T/S
Function
PCI Address and Data: 32 bit multiplexed address/data bus. PCI Bus Command and Byte Enables: Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. Master drives PAR on address cycles and PCI writes. The Target drives PAR on PCI reads. PCI Cycle Frame: Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction.
PAR
T/S
FRAMEN DEVSELN CLK RSTN PERRN SERRN IDSEL IRDYN TRDYN STOPN
S/T/S
S/T/S PCI Device Select. Driven by a Target that has decoded a valid base address. IN IN S/T/S O/D IN S/T/S S/T/S PCI System Clock Input. PCI System Reset Input PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BEN busses. PCI System Error: Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select. Use to select a specific PCI Agent during System Initialization. PCI Initiator Ready. Indicates the Initiator's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready. Indicates the Target's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active.
S/T/S PCI Stop. Used by a PCI Target to end a burst transaction.
14.0 Ordering Information
QL 5030 - 4 TQ144 C QuickLogic device Operating Range C = Commercial I = Industrial Package Code TQ144 = 144-pin TQFP
QuickPCI device part number Speed Grade 4 = Quick
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(c) 2002 QuickLogic Corporation
QL5030 QuickPCI Data Sheet
15.0 144 TQFP Pinout Diagram
PIN #109 PIN #1
QuickPCI QL5030-33APF144C
PIN #37
PIN #73
16.0 144 TQFP Pinout Table
Table 17: 144 TQFP Pinout Table
PF144
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function
I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC RSTN CLK VCC I/O AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] GND AD[25] AD[24] CBEN[3] IDSEL AD[23] AD[22]
PF144
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Function
AD[21] TDI/RSI AD[20] AD[19] AD[18] VCC AD[17] AD[16] CBEN[2] FRAMEN IRDYN TRDYN DEVSELN GND STOPN PERRN SERRN GND PAR CBEN[1] AD[15] VCCIO AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] TRSTB/RRO TMS
PF144
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Function
AD[4] AD[3] AD[2] AD[1] AD[0] I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I ACLK/I VCC GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
PF144
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Function
TCK STM I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO/RCO I/O
QL5030 QuickPCI Data Sheet Rev C
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QL5030 QuickPCI Data Sheet
17.0 Revision History
Table 18: Revision History Revision
A B C
Date
Sept 1999 March 2001 Jan 2002
Comments
First release. Update of electrical specs Re-formatted and re-organized for better clarity
Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc.
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(c) 2002 QuickLogic Corporation

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